PhD defense of Björn Hult, 11th September 2025

Björn Hult will defend his thesis, “Downscaled III-Nitride Power HEMTs with Thin GaN Channel Layers: Fabrication, Characterization, and Physics-Based Modeling”,  at 9 am on September 11th, 2025, in Kollektorn, Kemivägen 9, Göteborg. The faculty opponent is Dr. Oliver Hilt, Head of Department, Ferdinand-Braun-Institut, Germany.

The thesis is available here:   https://research.chalmers.se/publication/547840

Abstract:

The unique polarization properties of the III-nitride materials have motivated research into gallium nitride (GaN)-based high-electron-mobility transistors
(HEMTs) for both power electronics and microwave applications. In these devices, compensation-doped buffer layers and strain-relief layers are typically incorporated into the III-nitride layer stack to reduce off-state currents and to achieve high-crystal-quality GaN and aluminum GaN (AlGaN) layers. However, thin-channel AlGaN/GaN/AlN heterostructures have been presented as a viable alternative to the conventional technology. Among these types of heterostructures, the buffer-free´QuanFINE® concept has been suggested. This material uses the AlN nucleation layer and the silicon carbide substrate to improve the electron confinement in the GaN channel layer. In this thesis, high-voltage buffer-free GaN power HEMTs are evaluated.

The devices are characterized in terms of their on-state, off-state, and dynamic performance. The impact of critical processing modules – including isolation techniques, dielectrics, and field plate configurations—is investigated. Due to the high electron confinement in the GaN channel layer, a power figure of merit of 729 MW/cm2 at sub-100 nA/mm drain-source current could be achieved, which is comparable to most state-of-the-art technologies reported in the literature. In contrast to heterostructures with buffer designs, no compensation dopants that can adversely affect the dynamic performance are intentionally incorporated into GaN or AlN layers. However, it is not fully understood how, or to what extent, unintentional defects and impurities will affect the dynamic performance in buffer-free HEMTs. A physics-based technology computer-aided design model is presented to explain the capture and emission processes involved during and after high-voltage conditions. It is hypothesized that a highly ionized donor concentration exists in the GaN layer near the GaN/AlN interface. The trap is thought to be related to defects and impurities that naturally coalesce near the GaN/AlN interface. These states are needed to prevent a semi-permanent current reduction after high-voltage conditions. However, it is also shown that the spatial distribution has to be controlled to prevent excessive off-state drain-source leakage currents.
An alternative measurement technique for estimating drain-induced barrier lowering in GaN HEMTs is also suggested. The new method is based on the drain
current injection technique (DCIT), which facilitates the measurement of threshold voltage variations at different drain-source voltages. GaN HEMT with short gate lengths (LG) and different epitaxial designs were used to demonstrate the viability of the method. For high-voltage buffer-free HEMTs, the DCIT can be used in the optimization of channel layer thickness and LG to improve dynamic performance while minimizing the adverse effects of LG reduction. Overall, the thesis contributes to the advancement of III-nitride technologies tailored toward power applications through the development of thin-channel buffer-free materials.

PhD defense of Ragnar Ferrand-Drake Del Castillo, 4th Sept 2025

Ragnar Ferrand-Drake Del Castillo will defend his thesis, “Trapping Effects in Gallium Nitride High Electron Mobility Transistors: Mechanisms, Modeling, and Applications” at 9 am on September 4th, 2025, in Kollektorn, Kemivägen 9, Göteborg. The faculty opponent is Stephane Piotrowicz, III-V Lab, France.

The thesis is available here:  https://research.chalmers.se/publication/?created=true&id=682b82af-56e5-4dcd-b9e0-4a5e069d4c55

Abstract:

While GaN-based high-electron-mobility transistors (HEMTs) have become indispensable for 5G and RADAR systems, they also show potential for astronomy and space exploration. Knowledge gaps remain in how epitaxial and processing design impact device performance. Downscaling of GaN HEMTs exacerbates source-drain current dispersion due to trapping and self-heating effects. This thesis focuses on characterizing and optimizing back-barrier/buffer design and processing methods to mitigate trap-induced degradation.
Although back-barrier and buffer doping individually enhance two-dimensional electron gas (2DEG) confinement, carbon-induced trapping creates a trade-off between confinement and dispersion. This work explores variations in carbon doping levels in the GaN buffer and AlGaN back-barrier to improve 2DEG confinement. By employing extensive electrical and spectroscopic methods, trapping mechanisms and their origins are investigated. The results show that dispersion dominates over short-channel effects at the investigated carbon levels, offering guidance for RF performance optimization. Annealing during gate opening is widely used to counteract damage from fluorine-based plasma treatments. However, the influence of high-temperature pre-gate annealing (500−800◦C), particularly in relation to CF4 and CF4 chemistries, remains underexplored. This study demonstrates that fluorine implantation and surface oxidation affect device behavior via thermally activated and deactivated traps. It identifies optimal combinations of fluorine plasma and annealing treatments, showing that up to 60 % of CF4 plasma-induced F−states can be deactivated by 600◦C annealing. Buffer trapping is also studied under cryogenic conditions, where Fe-induced traps manifest slow de-trapping dynamics. Field plates are found to mitigate these effects, emphasizing epi-structure and layout design strategies critical for reliable cryogenic GaN HEMT operation.
This thesis further shows that charged states introduced during gate-defining processing can be deliberately harnessed to modulate reverse gate-bias C–V characteristics. By varying fluorine plasma chemistry and pre-gate annealing conditions, the distribution and concentration of charged states in the barrier/channel region can be tuned. This enables the development of GaN-based varactors for MMIC applications, offering low nonlinear distortion in RF systems. By addressing key challenges in reliability and performance, and exploring emerging applications such as cryogenic operation and varactor integration. This thesis is well placed to advance and diversify GaN HEMT technology.

PhD Defense Ding-Yuan Chen

Ding-Yuan Chen will defense his PhD Thesis

“Ohmic Contacts, Passivation, and Buffer-Free Concepts”

Date: February 7th 2025, 10:00 am

Location: Chalmers University of Technology, Kemivägen 9, Kollektorn

Online: N/A

Supervisor: Niklas Rorsman, Chalmers University of Technology

Opponent: Dr. Farid Medjdoub, CNRS senior scientist, Group leader, IEMN, France

Licentiate Defense Viktor Rindert

Viktor Rindert will defense his Licentiate Thesis

“Terahertz Electron Paramagnetic Resonance Spectroscopic Ellipsometry”

Date: January 31st 2025, 10:15 am

Location: Lund University, Division of Solid State Physics, k-space

Online: N/A

Supervisor: Vanya Darakchieva, Lund University

Opponent: Docent Jan Eric Stehr, Dept. of Physics, Chemistry and Biology, Linköping University, Sweden

C3NiT Day 2024 in Lund – final program and registration for on-site participation

C3NiT Day 2024 Header

Welcome to the C3Nit Day 2024 in Lund on the 20th of November.

Venue

Venue: Lund University, House “M” Meeting room “Teknodromen”. Address: Ole Römers väg 1 / Klas Anshelms väg 4, 223 63 Lund 

Program

09.30        Welcome, Vanya Darakchieva, Centre Director & Erik Lind, Vice-Centre Director, LU

09.40        Invited talk: “Wide Bandgap Semiconductor Based Devices and Applications”, Qin Wang, RISE/KTH

10.10       Project I / II / III: Linear and E/W/D-band HEMTs and MMICs, Mattias Thorsell, Saab and Niklas Rorsman, Chalmers

10.40        Break

11:00        Industrial relevance I: Mikael Björk, Hexagem AB 

11:15        Invited talk: “Power Electronics in Automotive Applications“, Mats Alaküla, LTH

11:45        Poster Pitches

12.15         Lunch break

13.10        Short talks

13.40        Project IV: Vertical devices for power application, Muhammad Nawaz, Hitachi Energy

14.00        Invited talk: “The Swedish Chips Act Competence Center“, Lars Palm, LU

14.30        Break

14.45        Poster session

16.00        Industrial relevance II: Herman Stieglauer, UMS GmbH

16.15        Project V: Propulsion/Charger/Converter/Switching applications, Pengpeng Sun, Volvo/Chalmers

16.35        Project VI: Advanced epitaxial concepts for cost reduction and high performance, Vanya Darakchieva, LU

16.55        Closing Remarks, Niklas Rorsman, Chalmers

17.00       End of program

19:00                   Dinner
Venue: Taperian, Stadshallen Lund, Stortorget 9, 222 23 Lund

Please register for on-site participation at the link below by Friday the 15th of November

Registration for on-site participation

Article in Elektroniktidningen about our role in the WBG pilot line

You can read the complete article at this link: https://issuu.com/etndigi/docs/etn2405ld/6

In short, this is about three universities, three materials with wide bandgaps. Gallium nitride, gallium oxide and aluminium nitride will be the focus of Lund, Chalmers and Linköping within the EU’s fourth pilot line.
The materials have a wider band gap than silicon carbide but are not as mature.
“The three of us have worked together for a long time in Vinnova’s competence centre C3NiT. That’s why we were invited to join. The collaboration is unique because it covers everything from materials to systems,” says Professor Vanya Darakchieva, chair of C3NiT.
Lund is officially responsible for WP6, the entire Swedish part of the EU’s fourth pilot line within the EU research programme Chips Joint Undertaking which also includes KTH’s part that focuses on silicon carbide.
“The three of us will be responsible for epitaxy on gallium nitride, gallium oxide and aluminium nitride but also for manufacturing some components.
“Lund is in a good position because we have received a substantial amount of money for equipment for wide bandgap materials over a long time,” says Vanya Darakchieva.
Among the donors are the Olle Engkvist Foundation and the Wallenberg Foundations. A small part of the funding will go towards upgrading the cleanroom in Lund with machines dedicated to the pilot line. These include a direct laser writer and a probe station for higher powers. A new MOCVD machine is also needed to perform epitaxy on four-inch gallium oxide discs.

C3NiT Day 2024: 20th November in Lund

This is a pre-announcement and a warm invitation to join us for the C3NiT Day 2024 on Wednesday the 20th November in Lund.

As usual, the program will include research results from the 6 C3NiT projects, industrial talks, invited speakers and more.

More information will come, for the moment, please block the date.

C3NiT has a leading role in European Chips Act

Many in Europe have been eagerly awaiting the results of the first calls in the European Chips Act for pilot lines, with the aim to enhance existing and develop new advanced pilot lines across the Union to enable development and deployment of cutting-edge semiconductor technologies and next-generation semiconductor technologies.

The C3NiT research groups at Linköping, Chalmers and Lund University also have a stake in the call and we were very happy when the Chips JU announced that the Public Authories Board approved all four pilot line proposals.

Vanya Darakchieva will lead the Work-package on III- N radiofrequency and power device technologies of the Wide Bandgap pilot-line. The total budget of the three universities will comprise a total effort of over 16 M€ over 5 years.

“It is a great honour to be internationally recognized for our leading role in research on wide-bandgap materials for power electronics. We are happy and eager to work together with European partners and industries for establishing a resilient wide band gap semiconductors ecosystem” says Vanya Darakchieva.

For the research groups in C3NiT, the contribution to the Wide Bandgap pilot line is based on the equipment available in the three cleanroom labs as well as expertise in III-Nitride and gallium oxide materials synthesis and characterization. The III-Nitride activities are focussed on the developments of state-of-the-art epitaxy, radio-frequency and power HEMTs and FinFETS. The target applications for power devices include smart grid, electric train traction, wind turbines, power components for propulsion and charging of electric vehicles. The III-nitrides rf electronic devices target power generation and amplification at high frequencies above 100 GHz for future wireless communication infrastructure, and for transmitters as well as rugged and linear receivers for surveillance and security systems.

Through the industrial collaboration within C3NiT the pathway to innovation where these technologies lead to an actual benefit in society is facilitated.

The EU Chips act is a key step for the EU’s technological sovereignty and an investment of close to 11 billion € in Europe’s competitiveness and resilience in semiconductor technologies and applications and help to achieve both the digital and green transition. In force since 13 September 2023, one of its first actions focussed on advanced pilot lines.

The proposal is coordinated by the Italian National Research Council (CNR) and includes partners from France, Poland, Finland, Germany, Austria and Sweden.

Short Facts – Pilot lines
Their purpose is process development, test and experimentation, as well as small-scale production. In practise, the pilot line will be a distributed infrastructure with local nodes that are specialized on specific processes within the semiconductor value chain. In this case for example, the Polish partners are producing some of the bulk materials, the Swedish partners are developing SiC bipolar and GaN radiofrequency and power device technologies, the Finnish partners are responsible for packaging and integration. Guidance for external users on how to work with this process flow will be provided.